Exploration of Silicon Microprocessors

Thomas Hollowell

University of Rochester Optics 307 - SEM Practicum

April 2014

Introduction

Microchips have been important to the lives of everyone viewing this website but their inner structure has remained a mystery to me despite their proliferation. Aside from being magnificent pieces of technology, microchips have interesting surface and subsurface structures to image with the scanning electron microscope and provide an exciting opportunity to examine the result of decades and billions of dollars of research.

At the microscale, processors are have millions of circuit traces and numerous layers conducting current between transistors. My exploration seeks to observe multiple layers, the connections between them, surface features and their size (for comparison to Moore's Law) and the intricate interface between the processor and surrounding electronics.

Depackaging, Preparation and Cleaning of Pentium Pro Processor

Removing the processor from its protective casing was somewhat difficult. The initial solder bond holding the cover seen in Figure 1 took some time to melt and be pried off.

Figure 1: Pentium pro Chip prior to depackaging

Once the cover was removed, light microscopy began. However, a thin, stubborn layer of polyimide was present over the surface of the chip. This protective layer was visible in color and was quite difficult to remove. Several hours of Oxygen plasma ashing was insufficient to remove the layer. Solvents were tried including Ethanol, Methanol, Acetone and Ethidium bromide. None of these were effective, so several hours of soaking NaOH was employed to break the polyimide down. This was sufficient along with mechanical cleaning and further plasma cleaning to remove nearly all the surface polyimide. (See Figures 2, 3)

Figure 2: Residual polyimide blobs on chip surface (20x)

Figure 3: Residual polyimide streaks on chip surface (5x)

Further prep was necessary to minimize the size of the processor and fully eliminate charging. Initially the edges surrounding the IC faces were heavily padded with conductive tape and corners grounded with conductive paint, but this was insufficient - mild charging remained for all apertures but the 10um (smallest). Sputtering a ~40&#Aring; thick gold layer on the surface reduced the charging to negligable without obscuring any surfaces. (Note - Xray spectrometry detected almost no gold so composition analysis was not degraded.

Light Microscopy

Prior to imaging the processor in the SEM, visible light imaging was employed to observe surface features, inspect the chip edges and connections and observe potential areas of interest for imaging with the SEM. Additionally, Silicon Graffiti was searched for. Enough time was spent to get familiar with the layout of all portions of the chip, but no graffiti was discovered.

Figure 4: Intel Logo and year in chip corner (10x)

Figure 5: Contacts and connecting wires on chip edge

Figure 6: Upper level of Aluminum traces caps lower level - with window (50x)

Figure 7: Changing the focus reveals underlying logic gates

Scanning Electron Microscopy (Secondary Electron, InLense, Backscatter techniques)

The bulk of the imaging time was carried out on the SEM. While it is more troublesome to have a sample prepared for SEM imaging, the SEM allows compositional analysis, extremely high magnification imaging and large depth of field within a single image.

Advantages to each technique:

• Secondary Electron
Secondary Electron (or SE2) images have the most surface detail and excellent contrast. It is possible to see edges, slopes and valleys on the sample due to the bias of the detector to pick up more electrons originating from the side of a "hill" closer to the sensor.
Secondary electrons are produced when the accelerated electron beam collides and interacts with the surface of the sample
• In Lense
(also senses Secondary Electrons - in a different location) InLense images are similar to SE2 images, but have a flatter, less biased character since all electrons take off vertically to reach the detector.
• Backscatter
Backscattered electrons are arise from a fundamentally different process than Secondary Electrons. While secondary electrons are distinct and much lower energy than the beam electrons, Backscatter electrons are the same electrons which previously traveled in the beam. They are then backscattered (think "reflected") toward the detector at nearly the same energy as the beam itself.
This technique provides a basic idea of the atomic number of regions of the sample since high-Z elements backscatter much more than low-Z elements.

Images were taken at electron accelerations between 5 kV and 20 kV for various purposes - low accelerating voltage is good for seeing surface detail, high accelerating voltage provides information about layers below the surface and improves X-Ray spectrometry - especially X-Ray maps.

Figure 8: Division in circuit traces shows both valleys and surface areas still covered in polyimide after extensive cleaning (SE2, 6kx)

Figure 9: Overview of fractured surface

Figure 10: Secondary Electron closeup of Via Ports (5.6 kx)

Figure 11: Colorized image highlighting Via plugs. InLens Image used as colorization layer

X-Ray Mapping

Figure 12: InLens Electron closeup of Via Ports (4.4 kx) Corresponding to following X-Ray maps.

Figure 13: Tungsten Map distinctly highlights Via Ports as Tungsten!

Figure 14: Silicon Map shows silicon distributed throughout image - especially on perpendicular face

Figure 15: Oxygen Map shows what is probably a deposited oxide layer along edge

Figure 16: Titanium map shows assorted bits of Ti.

The X-ray maps show low resolution depictions of the location of selected elements present in the sample. High accelerating voltage is used to create many interactions between the electron beam and sample matter.
Here Silicon and Tungsten are especially interesting. Silicon is clearly present throughout the sample, though darker areas in the Secondary electron images are less present in the X-ray map as well. More exciting is the clear presence of heavy metal Via Ports linking different layers of the chip. These are buried several µm deep in the surface and aren't noticeable when imaging from the top.

Stereo Anaglyph

Figure 17: Stereo Anaglyph showing fractured features and Vias.
(3° separation between left and right)

Electron Flight Mapping

Figure 18: Silicon 0° angle

Figure 19: Silicon 50° angle

Figure 20: Silicon Dioxide 0° angle

Figure 21: Silicon Dioxide 50° angle

Acknowledgements

Very much thanks is due to Brian McIntyre for helping me with project selection, sample preparation, choosing intersting areas to image, help troubleshooting simple and complex problems and interpreting my results. Lessons learned were not limited to SEM.
In addition, of course, the opportunity to learn in this class was especially unique and may be something I don't get to enjoy again, so a heartfelt thanks for this wonderful opportunity to explore a world normally unseen!