Since the end of 1940s, when John Bardeen, Walter Brattain and William Shockley invented the transistors, we have been on the way of electronics. In 1958, Jack Kilby from Texas Instrument, developed the first integrated circuit , and in 1959, Bob Noyce from Fairchild made IC independently. And their work initiated the electronic revolution. In 1965, Gordon Moore from Fairchild Semiconductor made a predict which was enshrined as the Moore's Law later, the MOS density will double every 18 months. In fact, this is not a law at all, rather, it is a cadence which gave the impetus to the industry. In the past four decades, the MOS technology has played the main role in the IC field, first MOSFET and now CMOS. And the feature size has shrinked down to 35 nm. And new microfabrication techniques are adopted to achieved that. [1]

In this project, an intel i486 chip is adopted. We used a hotplate to heat it and then peel off the metal cover, which is known as a depackaging process. Then a plasma etcher is adopted to remove the polymer on the surface of the chip. And the IC sample through different microscope techniques, including Light Microscope, SEM and AFM. Also, EDAX is used to analyze the composition of the surface polymer.

Sample Preparation

The integrated circuit is packaged in the ceramic, and the circuit area only accounts for a small area of the whole chip. To observe the inner structure of the chip, we need to depackage it. There are two typical methods to achieve this. Usually, it depends on what kind of material the package is. For the plastic cover, the chemical solution is used to etch the package; however, for a ceramic, we usually heat it to melt the sticky gel and then remove the metal cover. And in this project, a heating plate is adopted and some physical damage is made so that we can peel off the metal cover more easily.

Also, there are usually a layer of polymer on top of the circuit. If we put the chip into the chamber and let the electron beams hit the surface directly, there will be a lot of charging, also, it may not be able to show the detail of the circuit itself but the topography of the polymer. In this project, we use a plasma etching machine, which will generate oxygen plasma and the ions will hit the surface of the chip and etch away the polymer.

The Inner Scenario of the Integrated Circuit



Microscopy Images

Light Microscopy Imaging

When the requirement of the resolution is not so high, then we can use a light microscope to observe the sample at the very first beginning to get an initial scope of the chip. And with the olympus light microscope in the lab, we use a 10x objective lens and we only need to move the sample to the middle of the focal plane and then change the working distance to get the focused image. The depth of the field can be noticed. And the collected image is captured through a solid state image sensor array.

Two Light Microscopy Images of the Sample, different area with magnification around 50x.



Secondary Electron (SE) Imaging

The accelerating voltage is set to be 20KV, so that the electeon beam can penetrate the remainig polymer on the surface and show much more details of the circuits themselves. And for the microscopy of the topography of the surface of this intergrated circuit , the magnificaiton is set to be around 400x, and in such a magnification, the image will show the pattern of the wire while neglect the tiny fracture, defects or toppings over the wire.

400x images - The SE2 Images of the Integrated Circuits



The Polymer on the Surface

However,when we magnify the images to around 5kx, the world will be different. The remaining polymer shows up and take a look like the beautiful snowflakes. And we use both SE2 and inlens detector to take images of them, which is so exciting!

5kx images - The Microscope Images of the Polymer on the Surface




X-Ray Spectroscopy The EDAX

Now that we find the "toppings" on the surface of the circuit, we make use of the EDAX technique to sketch the X-Ray Spectroscopy. And we repeat the collection process for twice in two different areas and the spectroscopy is shown as following. It seems that more than the silicon and oxygen, which is common guys in the ICs, there are also peaks of Aluminum and Nitride, so we may guess that the polymer is the compound of Aluminum and Nitride or something else:)

The X-Ray Spectroscopy of the Polymer



Atomic Force Microscopy

We use the semi-contact mode of the AFM to sketch a 30 by 30 microns area of the topography of the ICs. The semi-contact will have the tip vibrate at some resonant frequency and then as it get closer to the surface of sample, its resonance will be affected by the atomic force from the surface. And the laser will be defected from the center of the detector, which will be kept down as the information of the height of the surface. In this project, the tip seems to encounter a lot of noise which may come from the amorphous polymer remained in the surface. However, we can still discern the grooves there. Also, with the help of AFM data analysis tool, we make a simple 1 dimensional analysis, the target line is shown in the figure with blue line, and the relative depth along the line is plotted. We can find two valleys clearly.


The AFM Microscopy Images ---- 30 x 30 microns




3D Demonstration of the Circuits

3D image is different from a 2D image which is flat. So,in stereo image, you need to take two images from different angle and then merge them together to provide the depth information. Usually, there are 6 to 10 centimeters difference between two eyes. However, in this project, we make use of the rotation method, which take two images with 5 degrees deviation. And this method provides a similar with the effects as the shifted images collected by two eyes.


The 3D Image




Through microscope techniques, we are able to find the detail of the integrated ciruits. The circuits are designed block by block, which is just like the arrangement of a metropolitan with square areas; The typical line width of this chip is around 10 microns, and do remember, this is a product of 1989. In modern days, the line width is much narrower and the typical feature size is around several nanometers.In this project, we have only imaged the topography of the chip, however, the chip itself is a sandwich and has its layered structure. And to use microscope to do reverse circuits structure analysis, we cannot ignore the layer information. However, we cannot go that far in this project, which is a little pity


1. Howard Huff, Into the Nano Era, Springer-verlag Berlin Heidelberg (2009), Inc.

2. Randy Torrance, Dick James, The state-of-the-art in IC reverse Engineering



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